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71M6545/71M6545H Data Sheet
2.4
2.4.1
80515 MPU Core
MPU Setup Code
For the proper operation of the 71M6545/H, it is necessary to have a small MPU program in flash
memory. In a typical application, the external host processor performs all post-processing and monitors
and controls the 71M6545/H over its SPI slave interface. The following is a brief description of the tasks
performed by the required setup code. The setup code correctly configures the 71M6545/H to act as an
SPI Slave to a host processor, providing powerful AFE and 32-bit Metrology Processor functionality.
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The main objective of the setup code is to keep the MPU code execution confined to a small area
of Flash memory.
Most of the Flash memory space is empty, except for the small setup program and the CE code.
When ac power failure occurs, the MPU sets the SLEEP bit ( I/O RAM 0x28B2[7] ) bit) to force the
device to SLP mode (see 3.2 SLP Mode (Sleep Mode) on page 66 ).
SFR (Special Function Registers) access is needed for configuring and controlling the DIO0-
DIO14 pins. The SFRs of the MPU cannot be accessed directly over the SPI Slave interface. If
the host requires control of DIO0-DIO14, a small amount of code in the MPU provides the needed
SFR access.
Triggering the WDT reset.
Controlling the 71M6xx3 Remote Sensor Interfaces, if used (temperature data for CE).
To speed up the start-up process and to offload the host processor, the small MPU program can
implement the following optional steps at start-up:
- Copy CE data from flash to XRAM (default settings).
- Initialize the interrupt vector table.
- Initialize the pointer to the CE code location.
- Initialize the environmental settings for the CE code (multiplexer and filter settings, etc.)
- Start the ADC and CE.
It is also recommended that the small MPU program maintains a counter that is incremented with
each XFER_BUSY interrupt. By reading this counter, the external host processor can determine if
any accumulated metrology data were missed and if the 71M6545/H code is executing as
expected.
Sample MPU code that performs these simple tasks is available from Maxim.
During normal operation, the host processor needs to trigger the watchdog reset periodically in order to
avoid watchdog resets, if this is not done by the MPU program inside the 71M6545/H.
The remainder of this section provides detailed information concerning the MPU, and may be
ignored if the application does not require the use of the MPU beyond the simple setup code tasks
described.
2.4.2
80515 MPU Overview
The 71M6545/H includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one
clock cycle. Using a 4.9 MHz clock results in a processing throughput of 4.9 MIPS. The 80515 architecture
eliminates redundant bus states and implements parallel execution of fetch and execution phases. Normally, a
machine cycle is aligned with a memory fetch, therefore, most of the 1-byte instructions are performed in a
single machine cycle (MPU clock cycle). This leads to an 8x average performance improvement (in terms of
MIPS) over the Intel ? 8051 device running at the same clock frequency .
Table 8 shows the CKMPU frequency as a function of the MCK clock (19.6608 MHz) divided by the MPU
clock divider MPU_DIV[2:0] (I/O RAM 0x2200[2:0]) . Actual processor clocking speed can be adjusted to
the total processing demand of the application (metering calculations, AMR management, memory
management and I/O management) using MPU_DIV[2:0] , as shown in Table 8 .
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